PMC

a) Retention characteristics of both on‐ and off‐state up to 5 × 10⁴ s with the duration of program and erase gate bias of 1 s. b) Program and erase endurance cycles of the device. V _gs = 0 V, V _ds = 1 V. For clarity, one cycle out of every 10 is plotted. c) Current dynamics of the memory cell, V _ds = 0.1 V. d) SEM image of the memory inverter circuit. Scale bar is 2 μm. e) Transfer characteristics of the transistor constructed in our inverter circuit. Inset shows the equivalent circuit diagram of the inverter circuit. f) VHCs of the memory inverters with different resistor types R₁ and (R₁+R₂), obtained at V _DD = 1 V.

(a) Optical images and (b) schematic illustration of the SiNW CMOS inverter on a transparent substrate. Reproduced from []. (c) Schematic of a SiNW-FET-based charge-trapping non-volatile flash memory; (d) TEM image of the cross section of a MATATOS device. Inset demonstrates the typical thickness of the top gate stack. Reproduced from [].

a The change in transfer characteristics of the flash memory according to time after the optimum programming state (programming voltage (V_prg) =  + 19 V) and b drain current (I_D) at gate voltage (V_G) = 1 V and I_D = 2 V versus time in the programming (open symbol) and erasing (closed symbol) states. c The comparison of the retention characteristics and programming voltage/erasing voltage (V_prg/V_ers) of the flash memory in this study to those based on polymer dielectrics in the previous reports. d The change in transfer curves of the flash memory according to time and the transfer curve of the heterojunction transistor (HTR). e The change in voltage transfer characteristics (VTCs) and f intermediate logic value of the 3-dimensional (3D) ternary logic inverter (T-inverter) according to time. g The VTCs of 100 consecutive sweeps of the 3D T-inverter with the optimum programming states, and h output voltage (V_OUT) values at input voltage (V_IN) = 0, 3.25, and 5 V extracted from each cycle.

a TEM cross-section^, and b schematic cross-section of an 28 nm high-κ metal gate FeFET device. c I_D–V_G characteristics of 60 different FeFETs measured after ±4 V, 1 μs write pulses. Good control over the device variability and a memory window of 1.2 V are demonstrated. d The dynamic switching characteristics of the FeFET as a function of write pulse width at different pulse amplitudes. Tradeoff between amplitudes and pulse widths are present. e Schematic of the proposed active interconnect based reconfigurable encryption block. f Buffer mode configuration. g Inverter mode configuration. h Simulated waveforms in buffer mode showing the programming and logic modes. i Simulated waveforms in inverter mode. j Applied voltages on the encryption block in experiment. k The applied waveform for functionaltiy verification in experiment. l, m Captured transient waveforms in the logic evaluation mode for buffer and inverter modes, respectively. For all tested FeFETs, W/L = 500 nm/500 nm are used.